Download Digital Design 5TH Fifth Edition By M. Morris Mano, Michael D. Ciletti

Introduction

The edition  4TH   of  Digital Design,  the commercial availability of devices using digital technology to receive,  transmit information seems to have exploded. The digital devise  of various kinds offer new, competing features  daily day by day. Underneath the attractive graphical user interface of all of these devices sits a digital system that processes data in a binary format. The theoretical foundations of these systems have not changed much; indeed, one could argue that the stability of the core theory, coupled with modern design tools, has promoted the widespread response of manufacturers to the opportunities of the marketplace. Consequently, our refinement of our text has been guided by the need to equip our graduates with a solid understanding of digital machines and to introduce them to the methodology of modern design.  This edition of Digital Design builds on the previous four editions, and the feedback of the team of reviewers who helped set a direction for our presentation. The focus of the text has been sharpened to more closely reflect the content of a foundation course in digital design and the mainstream technology of today’s digital systems: CMOS circuits. The intended audience is broad, embracing students of computer science, computer engineering, and electrical engineering. The key elements that the book focuses include (1) Boolean logic, (2) logic gates used by designers, (3) synchronous finite state machines, and (4) data path controller design—all from a perspective of designing digital systems. This focus led to elimination of material more suited for a course in electronics. So the reader will not find here content for asynchronous machines or descriptions of bipolar transistors. Additionally, the widespread availability of web based ancillary material prompted us to limit our discussion of field programmable gate arrays (FPGAs) to an introduction of devices offered by only one manufacturer, rather than two. Today’s designers rely heavily on hardware description languages (HDLs), and this edition of the book gives greater attention to their use and presents what we think is a clear development of a design methodology using the Verily HDL.

Contents

1 Digital Systems and Binary Numbers 1

1.1 Digital Systems 1

1.2 Binary Numbers 3

1.3 Number‐Base Conversions 6

1.4 Octal and Hexadecimal Numbers 8

1.5 Complements of Numbers 10

1.6 Signed Binary Numbers 14

1.7 Binary Codes 18

1.8 Binary Storage and Registers 27

1.9 Binary Logic 30

2 Boolean Algebra and Logic Gates 38

2.1 Introduction 38

2.2 Basic Definitions 38

2.3 Axiomatic Definition of Boolean Algebra 40

2.4 Basic Theorems and Properties of Boolean Algebra 43

2.5 Boolean Functions 46

2.6 Canonical and Standard Forms 51

2.7 Other Logic Operations 58

2.8 Digital Logic Gates 60

2.9 Integrated Circuits 66

3 Gate‐Level Minimization 73

3.1 Introduction 73

3.2 The Map Method 73

3.3 Four‐Variable K-Map 80

3.4 Product‐of‐Sums Simplification 84

3.5 Don’t‐Care Conditions 88

3.6 NAND and NOR Implementation 90

3.7 Other Two‐Level Implementations 97

3.8 Exclusive‐OR Function 103

3.9 Hardware Description Language 108

4 Combinational Logic 125

4.1 Introduction 125

4.2 Combinational Circuits 125

4.3 Analysis Procedure 126

4.4 Design Procedure 129

4.5 Binary Adder–Subtractor 133

4.6 Decimal Adder 144

4.7 Binary Multiplier 146

4.8 Magnitude Comparator 148

4.9 Decoders 150

4.10 Encoders 155

4.11 Multiplexers 158

4.12 HDL Models of Combinational Circuits 164

5 Synchronous Sequential Logic 190

5.1 Introduction 190

5.2 Sequential Circuits 190

5.3 Storage Elements: Latches 193

5.4 Storage Elements: Flip‐Flops 196

5.5 Analysis of Clocked Sequential Circuits 204

5.6 Synthesizable HDL Models of Sequential Circuits 217

5.7 State Reduction and Assignment 231

5.8 Design Procedure 236

6 Registers and Counters 255

6.1 Registers 255

6.2 Shift Registers 258

6.3 Ripple Counters 266

6.4 Synchronous Counters 271

6.5 Other Counters 278

6.6 HDL for Registers and Counters 283

7 Memory and Programmable Logic 299

7.1 Introduction 299

7.2 Random‐Access Memory 300

7.3 Memory Decoding 307

7.4 Error Detection and Correction 312

7.5 Read‐Only Memory 315

7.6 Programmable Logic Array 321

7.7 Programmable Array Logic 325

7.8 Sequential Programmable Devices 329

8 Design at the Register

Tr a n s f e r L e v e l 351

8.1 Introduction 351

8.2 Register Transfer Level Notation 351

8.3 Register Transfer Level in HDL 354

8.4 Algorithmic State Machines (ASMs) 363

8.5 Design Example (ASMD Chart) 371

8.6 HDL Description of Design Example 381

8.7 Sequential Binary Multiplier 391

8.8 Control Logic 396

8.9 HDL Description of Binary Multiplier 402

8.10 Design with Multiplexers 411

8.11 Race‐Free Design (Software Race Conditions) 422

8.12 Latch‐Free Design (Why Waste Silicon?) 425

8.13 Other Language Features 426

9 Laboratory Experiments

with Standard ICs and FPGAs 438

9.1 Introduction to Experiments 438

9.2 Experiment 1: Binary and Decimal Numbers 443

9.3 Experiment 2: Digital Logic Gates 446

9.4 Experiment 3: Simplification of Boolean Functions 448

9.5 Experiment 4: Combinational Circuits 450

9.6 Experiment 5: Code Converters 452

9.7 Experiment 6: Design with Multiplexers 453

9.8 Experiment 7: Adders and Subtractors 455

9.9 Experiment 8: Flip‐Flops 457

9.10 Experiment 9: Sequential Circuits 460

9.11 Experiment 10: Counters 461

9.12 Experiment 11: Shift Registers 463

9.13 Experiment 12: Serial Addition 466

9.14 Experiment 13: Memory Unit 467

9.15 Experiment 14: Lamp Handball 469

9.16 Experiment 15: Clock‐Pulse Generator 473

9.17 Experiment 16: Parallel Adder and Accumulator 475

9.18 Experiment 17: Binary Multiplier 478

9.19 Verilog HDL Simulation Experiments

and Rapid Prototyping with FPGAs 480

10 Standard Graphic Symbols 488

10.1 Rectangular‐Shape Symbols 488

10.2 Qualifying Symbols 491

10.3 Dependency Notation 493

10.4 Symbols for Combinational Elements 495

10.5 Symbols for Flip‐Flops 497

10.6 Symbols for Registers 499

10.7 Symbols for Counters 502

10.8 Symbol for RAM 504

Appendix 507

Answers to Selected Problems 521

Index 539

 

 

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