Download Digital Integrated Circuits 2nd Edition By Jan M. Rabaey

Introduction

The concept of digital data manipulation has made a dramatic impact on our society. One has long grown accustomed to the idea of digital computers. Evolving steadily from mainframe and minicomputers, personal and laptop computers have proliferated into daily life. More significant, however, is a continuous trend towards digital solutions in all other areas of electronics. Instrumentation was one of the first noncompeting domains where the potential benefits of digital data manipulation over analog processing were recognized. Other areas such as control were soon to follow. Only recently have we witnessed the conversion of telecommunications and consumer electronics towards the digital format. Increasingly, telephone data is transmitted and processed digitally over both wired and wireless networks. The compact disk has revolutionized the audio world, and digital video is following in its footsteps

Table of content

PART I. THE FOUNDATIONS

CHAPTER 1: INTRODUCTION

A Historical Perspective

Issues in Digital Integrated Circuit Design

Quality Metrics of a Digital Design

Cost of an Integrated Circuit

Functionality and Robustness

Performance

Power and Energy Consumption

Chapter 2: THE MANUFACTURING PROCESS

Introduction

Manufacturing CMOS Integrated Circuits

The Silicon Wafer

Photolithography

Some Recurring Process Steps

Simplified CMOS Process Flow

Design Rules — The Contract between Designer and Process Engineer

Packaging Integrated Circuits

Package Materials

Interconnect Levels

Thermal Considerations in Packaging

Perspective — Trends in Process Technology

Short-Term Developments

In the Longer Term

CHPATER 3: THE DEVICES 3.1

Introduction

The Diode

A First Glance at the Diode — The Depletion Region

Static Behavior

Dynamic, or Transient, Behavior

The Actual Diode—Secondary Effects

The SPICE Diode Model

The MOS(FET) Transistor

A First Glance at the Device

The MOS Transistor under Static Conditions 3

Dynamic Behavior

The Actual MOS Transistor—Some Secondary Effects

SPICE Models for the MOS Transistor

A Word on Process Variations

Perspective: Technology Scaling

CIRCUIT SIMULATION

CHAPTER 4: THE WIRE

First Glance

Interconnect Parameters  Capacitance, Resistance, and Inductance

Capacitance

Resistance

Inductance

Electrical Wire Models

The Ideal Wire

The Lumped Model

The Lumped RC model

The Distributed rc Line

The Transmission Line

SPICE Wire Models

Distributed rc Lines in SPICE

Transmission Line Models in SPICE

Perspective: A Look into the Future

To Probe Further PART II. A CIRCUIT PERSPECTIVE

Chapter 5: THE CMOS INVERTER

The Static CMOS Inverter — An Intuitive Perspective

Evaluating the Robustness of the CMOS Inverter:

The Static Behavior

Switching Threshold

Noise Margins

Robustness Revisited

Performance of CMOS Inverter: The Dynamic Behavior

Computing the Capacitances

Propagation Delay: First-Order Analysis

Propagation Delay from a Design Perspective

Power, Energy, and Energy-Delay

Dynamic Power Consumption

Static Consumption

Putting It All Together

Analyzing Power Consumption Using SPICE

Perspective: Technology Scaling and its Impact on the Inverter Metrics 5.7

CHAPTER 6: DESIGNING COMBINATIONAL LOGIC GATES IN CMOS

Static CMOS Design 6

Complementary CMOS

Ratioed Logic

Pass-Transistor Logic

Dynamic CMOS Design

Dynamic Logic: Basic Principles

Speed and Power Dissipation of Dynamic Logic

Issues in Dynamic Design

Cascading Dynamic Gates

Perspectives

How to Choose a Logic Style?

Designing Logic for Reduced Supply Voltages

DESIGN METHODOLOGY INSERT C: HOW TO SIMULATE COMPLEX LOGIC GATES

Representing Digital Data as a Continuous Entity

Representing Data as a Discrete Entity

Using Higher-Level Data Models

DESIGN METHODOLOGY INSERT LAYOUT TECHNIQUES FOR COMPLEX GATES

CHAPTER 7: DESIGNING SEQUENTIAL LOGIC CIRCUITS

Timing Metrics for Sequential Circuits

Classification of Memory Elements

Static Latches and Registers

The Bistability Principle

Multiplexer-Based Latches

Master-Slave Edge-Triggered Register

Low-Voltage Static Latches

Static SR Flip-Flops—Writing Data by Pure Force

Dynamic Latches and Registers

Dynamic Transmission-Gate Edge-triggered Registers

C2MOS—A Clock-Skew Insensitive Approach

True Single-Phase Clocked Register (TSPCR)

Alternative Register Styles

Pulse Registers

Sense-Amplifier Based Registers

Pipelining: An approach to optimize sequential circuits

Latch- vs. Register-Based Pipelines

NORA-CMOS—A Logic Style for Pipelined Structures

Non-Bistable Sequential Circuits

The Schmitt Trigger 7.

Monostable Sequential Circuits

Astable Circuits

Perspective: Choosing a Clocking Strategy

PART III. A SYSTEM PERSPECTIVE

 CHAPTER 8: IMPLEMENTATION STRATEGIES FOR DIGITAL ICS

From Custom to Semicustom and Structured Array Design Approaches

Custom Circuit Design

Cell-Based Design Methodology

Standard Cell

Compiled Cells

Macrocells, Megacells and Intellectual Property

Semi-Custom Design Flow

Array-Based Implementation Approaches

Pre-diffused (or Mask-Programmable) Arrays

Pre-wired Arrays

Perspective—The Implementation Platform of the Future

To Probe Further DESIGN METHODOLOGY INSERT E:

CHAPTER 9: COPING WITH INTERCONNECT

Capacitive Parasitic

Capacitance and Reliability—Cross Talk

Capacitance and Performance in CMOS

Resistive Parasitic

Resistance and Reliability—Ohmic Voltage Drop

Electro migration

Resistance and Performance—RC Delay

Inductive Parasitics

Inductance and Reliability— Voltage Drop

Inductance and Performance—Transmission Line Effects

Advanced Interconnect Techniques

Reduced-Swing Circuits

Current-Mode Transmission Techniques

Perspective: Networks-on-a-Chip

CHAPTER 10: TIMING ISSUES IN DIGITAL CIRCUITS

Timing Classification of Digital Systems

Synchronous Interconnect

Mesochronous interconnect

Plesiochronous Interconnect

Asynchronous Interconnect

Synchronous Design — An In-depth Perspective

Synchronous Timing Basics

Sources of Skew and Jitter

Clock-Distribution Techniques

Latch-Based Clocking

Self-Timed Circuit Design

Self-Timed Logic – An Asynchronous Technique

Completion-Signal Generation

Self-Timed Signaling

Practical Examples of Self-Timed Logic

Synchronizers and Arbiters

Synchronizers—Concept and Implementation

Arbiters

Clock Synthesis and Synchronization Using a Phase-Locked Loop

Basic Concept

Building Blocks of a PLL

Future Directions and Perspectives

Distributed Clocking Using DLLs

Optical Clock Distribution

Synchronous versus Asynchronous Design

CHAPTER 11: DESIGNING ARITHMETIC BUILDING BLOCKS

Datapaths in Digital Processor Architectures

The Adder

The Binary Adder  Definitions

The Full Adder: Circuit Design Considerations

The Binary Adder: Logic Design Considerations

The Multiplier

The Multiplier: Definitions

Partial-Product Generation

Partial Product Accumulation

Final Addition

The Shifter

Barrel Shifter

Logarithmic Shifter

Other Arithmetic Operators

Power and Speed Trade-off’s in Datapath Structures

Design Time Power-Reduction Techniques

Run-Time Power Management

Reducing the Power in Standby (or Sleep) Mode

Perspective: Design as a Trade-off

CHAPTER 12: DESIGNING MEMORY AND ARRAY STRUCTURES

Memory Classification

Memory Architectures and Building Blocks

The Memory Core

Read-Only Memories

Nonvolatile Read-Write Memories

Read-Write Memories (RAM)

Contents-Addressable or Associative Memory (CAM)

Memory Peripheral Circuitry

The Address Decoders

Sense Amplifiers

Voltage References

Drivers/Buffers

Timing and Control

Memory Reliability and Yield

Signal-To-Noise Ratio

Memory yield

Power Dissipation in Memories

Sources of Power Dissipation in Memories

Partitioning of the memory

Addressing the Active Power Dissipation

Data-retention dissipation

Memory Design

The Programmable Logic Array (PLA)

A 4Mbit SRAM

A 1 Gbit NAND Flash Memory

Perspective: Semiconductor Memory Trends and Evolutions

 

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